CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 103

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.27
Datasheet
C1CYCTRKACT - Channel 1 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 1 CYCTRK ACT.
31:28
27:22
20:17
16:13
12:9
8:0
Bit
21
Access
RW
RW
RW
RW
RW
RW
RO
00000000
000000b
Default
Value
0000b
0000b
0h
0b
0h
0b
Reserved
ACT Window Count (C1sd_cr_act_windowcnt)
This configuration register indicates the window duration (in
DRAM clocks) during which the controller counts the number
of activate commands which are launched to a particular
rank. If the number of activate commands launched within
this window is greater than 4, then a check is implemented
to block launch of further activates to this rank for the rest of
the duration of this window.
Max ACT Check (C1sd_cr_maxact_dischk)
This configuration register enables the check which ensures
that there are no more than four activates to a particular
rank in a given window.
ACT to ACT Delayed (C1sd_cr_act_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two ACT commands to
the same rank.
Corresponds to tRRD at DDR Spec.
PRE to ACT Delayed (C1sd_cr_pre_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the PRE-ALL and ACT
commands to the same rank.
Corresponds to tRP at DDR Spec.
ALLPRE-to-ACT Delay (C1sd_cr_preall_act)
From the launch of a prechargeall command wait for these
number of clocks before launching a activate command.
Corresponds to tPALL_RP.
REF-to-ACT Delayed (C1sd_cr_rfsh_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between REF and ACT commands
to the same rank.
Corresponds to tRFC at DDR Spec.
0/0/0/MCHBAR
652-655h
00000000h
RO; RW
32 bits
Description
103