CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 128

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.12
128
TSMICMD - Thermal SMI Command
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register selects specific errors to generate a SMI DMI cycle, as enabled by the SMI
Error Command Register [SMI on Thermal Sensor Trip].
7:6
Bit
5
4
3
2
1
0
Access
RW
RW
RW
RW
RW
RW
RO
Default
Value
00b
0b
0b
0b
0b
0b
0b
Reserved
SMI on Catastrophic Thermal Sensor Trip (CATSMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on a
SMI on Hot Thermal Sensor Trip (HOTSMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on a
SMI on AUX3 Thermal Sensor Trip (AUX3SMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on an
SMI on AUX2 Thermal Sensor Trip (AUX2SMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on an
SMI on AUX1 Thermal Sensor Trip (AUX1SMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on an
SMI on AUX0 Thermal Sensor Trip (AUX0SMI)
0 = Disable reporting of this condition via SMI messaging
1 = Does not mask the generation of an SMI DMI cycle on an
catastrophic thermal sensor trip.
Hot thermal sensor trip.
Aux3 thermal sensor trip.
Aux2 thermal sensor trip.
Aux1 thermal sensor trip.
Aux0 thermal sensor trip.
0/0/0/MCHBAR
10E5h
00h
RO; RW
8 bits
Description
Processor Configuration Registers
Datasheet