CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 302

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.1
1.19.2
302
VER_REG - Version Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report the architecture version supported. Backward compatibility for the
architecture is maintained with new revision numbers, allowing software to load DMA-
remapping drivers written for prior architecture versions.
CAP_REG - Capability Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report general DMA remapping hardware capabilities.
63:56
31:8
7:4
3:0
Bit
Bit
55
54
Access
Access
RO
RO
RO
RO
RO
RO
000000h
Default
Value
Default
Value
1h
0h
00h
1b
1b
Reserved
Major Version number (MAX)
Indicates supported architecture version.
Minor Version number (MIN)
Indicates supported architecture minor version.
Reserved
DMA Read Draining (DRD)
0 = On IOTLB invalidations, hardware does not support
1 = On IOTLB invalidations, hardware supports draining of
DMA Write Draining (DWD)
0 = On IOTLB invalidations, hardware does not support
1 = On IOTLB invalidations, hardware supports draining of
Refer to the Intel VT-d specification Section 6.3 for
description of DMA draining.
Refer to the Intel VT-d specification.
0/0/0/DMIVC1REMAP
0-3h
00000010h
RO
32 bits
0/0/0/DMIVC1REMAP
8-Fh
00C9008020E30272h
RO
64 bits
draining of DMA read requests.
DMA read requests.
draining of DMA writes.
DMA writes.
(Sheet 1 of 5)
Processor Configuration Registers
Description
Description
Datasheet