CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 186

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

186
Bit
7
6
5
4
3
2
Access
RW-SC
RW
RW
RW
RO
RO
Default
Value
0b
0b
0b
0b
0b
0b
Extended Synch (ES)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
This mode provides external devices (e.g., logic analyzers)
monitoring the Link time to achieve bit and symbol lock
before the link enters L0 and resumes communication.This is
a test mode only and may cause other undesired side effects
such as buffer overflows or underruns.
Common Clock Configuration (CCC)
0 = Indicates that this component and the component at the
1 = Indicates that this component and the component at the
Retrain Link (RL)
0 = Normal operation.
1 = Full Link retraining is initiated by directing the Physical
This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
Link Disable (LD)
0 = Normal operation
1 = Link is disabled. Forces the LTSSM to transition to the
Writes to this bit are immediately reflected in the value read
from the bit, regardless of actual Link state.
Read Completion Boundary (RCB)
Reserved (FEDLB)
hard wired to 0 to indicate 64 byte.
exiting the L0s state and when in the Recovery state.
opposite end of this Link are operating with asynchronous
reference clock.
opposite end of this Link are operating with a distributed
common reference clock.The state of this bit affects the
L0s Exit Latency reported in LCAP[14:12] and the N_FTS
value advertised during link training.
Layer LTSSM from L0, L0s, or L1 states to the Recovery
state.
Disabled state (via Recovery) from L0, L0s, or L1 states.
Link retraining happens automatically on 0 to 1
transition, just like when coming out of reset.
(Sheet 2 of 3)
Description
Processor Configuration Registers
Datasheet