CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 167

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
Processor Configuration Registers
1.13.22
1.13.23
Datasheet
INTRLINE1 - Interrupt Line
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
INTRPIN1 - Interrupt Pin
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register specifies which interrupt pin this device uses.
7:0
7:0
Bit
Bit
Access
Access
RW
RO
Default
Default
Value
Value
01h
00h
Interrupt Pin (INTPIN)
As a single function device, the PCI Express device specifies
INTA as its interrupt pin. 01h=INTA.
Interrupt Connection (INTCON)
Used to communicate interrupt line routing information.
BIOS Requirement: POST software writes the routing
information into this register as it initializes and configures
the system. The value indicates to which input of the system
interrupt controller this device's interrupt pin is connected.
0/1/0/PCI
3Ch
00h
RW
8 bits
0/1/0/PCI
3Dh
01h
RO
8 bits
Description
Description
167

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