CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 235

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.15
1.16.16
Datasheet
ROMADR - Video BIOS ROM Base Address
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The IGD does not use a separate BIOS ROM, therefore this register is hard wired to 0’s.
CAPPOINT - Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:18
17:11
10:1
7:0
Bit
Bit
0
Access
Access
RO
RO
RO
RO
RO
Default
Default
Value
Value
0000h
000h
90h
00h
0b
RST/
RST/
PWR
PWR
Core
Core
Core
Core
Core
0/2/0/PCI
30-33h
00000000h
RO
32 bits
0/2/0/PCI
34h
90h
RO
8 bits
Capabilities Pointer Value (CPV)
This field contains an offset into the function's
PCI Configuration Space for the first item in the
New Capabilities Linked List, the MSI
Capabilities ID registers at address 90h or the
Power Management capability at D0h.
This value is determined by the configuration in
CAPL[0].
ROM Base Address (RBA)
Address Mask (ADMSK)
range.
Reserved
Hardwired to 0’s.
ROM BIOS Enable (RBE)
0 = ROM not accessible.
hard wired to 0's.
hard wired to 0’s to indicate 256-KB address
Description
Description
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