CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 91

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.12
Datasheet
C0CYCTRKRD - Channel 0 CYCTRK READ
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK RD Registers.
23:21
20:17
16:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RW
RW
RO
Default
Value
000b
00h
0h
0h
0h
0h
Reserved
Minimum Activate-to-Read Delay (C0sd_cr_act_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and READ
commands to the same rank-bank.
Corresponds to tRCD_rd parameter in the DDR3
specification.
Same Rank Write-to-Read Delayed (C0sd_cr_wrsr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and READ
commands to the same rank.
Corresponds to the tWTR parameter in the DDR3
specification.
Different Ranks Write-to-Read Delayed
(C0sd_cr_wrdr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the WRITE and READ
commands to different ranks.
Corresponds to the tWR_RD parameter DDR3 specification.
Same Rank Read-to-Read Delayed (C0sd_cr_rdsr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two READ commands to
the same rank.
Different Ranks Read-to-Read Delayed
(C0sd_cr_rddr_rd)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two READ commands to
different ranks.
Corresponds to the tRD_RD parameter.
0/0/0/MCHBAR
258-25Ah
000000h
RO; RW
24 bits
Description
91