CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 189

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.41
Datasheet
SLOTCAP - Slot Capabilities
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
PCI Express Slot related registers allow for the support of Hot Plug.
31:19
16:15
3:0
Bit
Bit
18
17
Access
Access
RW-O
RW-O
RW-O
RO
RO
Default
Default
Value
Value
0000h
0h
00b
1b
0b
Current Link Speed (CLS)
This field indicates the negotiated Link speed of the given PCI
Express Link.Defined encodings are:
0001b 2.5 GT/s PCI Express Link
All other encodings are reserved. The value in this field is
undefined when the Link is not up.
Physical Slot Number (PSN)
Indicates the physical slot number attached to this Port.
BIOS Requirement: This field must be initialized by BIOS to a
value that assigns a slot number that is globally unique
within the chassis.
No Command Completed Support (NCCS)
When set to 1b, this bit indicates that this slot does not
generate software notification when an issued command is
completed by the Hot-Plug Controller. This bit is only
permitted to be set to 1b if the hotplug capable port is able
to accept writes to all fields of the Slot Control register
without delay between successive writes.
Reserved for Electromechanical Interlock Present
(EIP)
When set to 1b, this bit indicates that an Electromechanical
Interlock is implemented on the chassis for this slot.
Slot Power Limit Scale (SPLS)
Specifies the scale used for the Slot Power Limit Value.
00:
01:
10:
11:
If this field is written, the link sends a Set_Slot_Power_Limit
message.
0/1/0/PCI
B4-B7h
00040000h
RW-O; RO
32 bits
(Sheet 1 of 2)
1.0x
0.1x
0.01x
0.001x
Description
Description
189