CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 221

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.15.12
Datasheet
DMILCTL - DMI Link Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Allows control of DMI.
15:8
6:3
1:0
Bit
7
2
Access
RW
RW
RO
RO
RO
Default
Value
00h
00b
0b
0h
0b
Reserved
Extended Synch (EXTSYNC)
0 = Standard Fast Training Sequence (FTS).
1 = Forces the transmission of additional ordered sets when
This mode provides external devices (e.g., logic analyzers)
monitoring the Link time to achieve bit and symbol lock
before the link enters L0 and resumes communication.
This is a test mode only and may cause other undesired side
effects such as buffer overflows or underruns.
Reserved
Reserved
Active State Power Management Support (ASPMS)
Controls the level of active state power management
supported on the given link.
00:
01:
10:
11:
exiting the L0s state and when in the Recovery state.
0/0/0/DMIBAR
88-89h
0000h
RO; RW
16 bits
Disabled
L0s Entry Supported
L1 Entry Enabled
L0s and L1 Entry Supported
Description
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