CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 18

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.2.1.1
1.2.1.2
1.2.1.2.1
1.2.1.2.2
18
DOS Range (0000_0000h – 0009_FFFFh)
The DOS area is 640 KB (0000_0000h – 0009_FFFFh) in size and is always mapped to
the main memory controlled by the GMCH.
Legacy Video Area (000A_0000h-000B_FFFFh)
The legacy 128-KB VGA memory range, frame buffer, (000A_0000h – 000B_FFFFh) can
be mapped to IGD (Device 2), to PCI Express (Device 1), and/or to the DMI Interface.
The appropriate mapping depends on which devices are enabled and the programming
of the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is
constant. The GMCH always decodes internally mapped devices first. Internal to the
GMCH, decode priority is:
Non-SMM-mode CPU accesses to this range are considered to be to the Video Buffer
Area as described above. The CPU will route these accesses on the non-coherent (NCS
or NCB) channels.
The GMCH always positively decodes internally mapped devices, namely the IGD and
PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI
Interface depends on the Legacy VGA configuration bits (VGA Enable & MDAP). This
region is also the default for SMM space.
Compatible SMRAM Address Range (000A_0000h-000B_FFFFh)
Unlike FSB platforms, the GMCH sees no SMM indication with CPU accesses. When
compatible SMM space is enabled, SMM-mode CPU accesses to this range route to
physical system DRAM at 000A_0000h - 000B_FFFFh. The CPU performs the decode
and routes the access to physical system DRAM.
PCI Express and DMI originated cycles to enabled SMM space are not allowed and are
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI
initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.
Monochrome Adapter (MDA) Range (000B_0000h-000B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI-Express,
or the DMI Interface (depending on configuration bits). Since the monochrome adapter
may be mapped to any of these devices, the GMCH must decode cycles in the MDA
range (000B_0000h - 000B_7FFFh) and forward either to IGD, PCI-Express, or the DMI
Interface. This capability is controlled by a VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the
GMCH decodes IO cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards
them to the either IGD, PCI-Express, and/or the DMI Interface.
1. IGD
2. PCI Express
3. DMI Interface (subtractive)
Processor Configuration Registers
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