CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 60

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

60
7:4
3:2
Bit
Access
RW-L
RO
Default
Value
00b
3h
Graphics Mode Select (GMS)
This field is used to select the amount of Main Memory that
is pre-allocated to support the Internal Graphics device in
VGA (non-linear) and Native (linear) modes. The BIOS
ensures that memory is pre-allocated only when Internal
graphics is enabled.
0h: No memory pre-allocated. Device 2 (IGD) does not claim
VGA cycles (Mem and IO), and the Sub-Class Code field
within Device 2 Function 0 Class Code register is 80.
1h-4h: Reserved.
5h-Dh: DVMT (UMA) mode, memory pre-allocated for frame
buffer, in quantities as shown in the Encoding table.
Eh-Fh: Reserved.
Note:This register is locked and becomes Read Only when
the D_LCK bit in the SMRAM register is set. This register is
also Intel VT-d lockable.
Hardware does not clear or set any of these bits
automatically based on IGD being disabled/enabled.
BIOS Requirement: BIOS must not set this field to 0h if IVD
(Bit 1 of this register) is 0.
Reserved
Encoding
(Sheet 3 of 4)
Dh
0h
5h
6h
7h
8h
9h
Ah
Bh
Ch
No memory pre-allocated
Processor Configuration Registers
Description
Description
160 MB
128 MB
256 MB
224 MB
352 MB
32 MB
48 MB
64 MB
96 MB
Datasheet