CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 304

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

304
21:16
15:13
Bit
23
22
Access
RO
RO
RO
RO
Default
Value
000b
23h
1b
1b
Isochrony (Isoch)
0 = Indicates this DMA-remapping hardware unit has no
1 = Indicates this DMA-remapping hardware unit has one or
To guarantee isochronous performance, software must
ensure invalidation operations do not impact active DMA
streams from such requesters. This implies that when DMA
is active, software perform page-selective invalidations
(instead of coarser invalidations).
Zero Length Read (ZLR)
0 = Indicates the remapping hardware unit blocks (and
1 = Indicates the remapping hardware unit supports zero
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability
supported by remapping hardware.
The Maximum Guest Address Width (MGAW) is computed as
(N+1), where N is the value reported in this field. For
example, a hardware implementation supporting 48-bit
MGAW reports a value of 47 (101111b = 2Fh) in this field.
If the value in this field is X, DMA requests to addresses
above 2^(x+1)-1 are always blocked by hardware.
Guest addressability for a given DMA request is limited to
the minimum of the value reported through this field and
the adjusted guest address width of the corresponding
page-table structure. (Adjusted guest address widths
supported by hardware are reported through the SAGAW
field).
Implementations are recommended to support MGAW at
least equal to the physical addressability (host address
width) of the platform.
Reserved
critical isochronous requesters in its scope.
more critical isochronous requesters in its scope.
treats as fault) zero length DMA read requests to write-
only pages.
length DMA read requests to write-only pages.
(Sheet 3 of 5)
Processor Configuration Registers
Description
Datasheet