CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 294

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.31
294
VTCMPLRESR - VT-d Completion Resource Dedication
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides a programmable interface to dedicate the DMI Completion
Tracking Queue resources to DMI VC0 Read, DMI VC0 Write, DMI VC1 and DMI VCp
Intel VT-d fetch and PEG Completion Tracking Queue resources to PEG VC0 read and
PEG VC0 write Intel VT-d fetch.
31:20
19:16
63:12
11:0
Bit
Bit
Access
Access
RW-L
RO-P
RO
RO
0000000000
Default
Default
Value
000h
Value
000h
000h
6h
Reserved
DMI VT-d Completion Tracking Queue Resource
Available (DMIVTCTRA)
Number of entries available in DMI VT-d Completion Tracking
Queue. 1-based. The values programmed in the fields below
must not be greater than the value advertised in this field.
Page Address (PADDR)
This field contains the address (page-granular) in the
faulted DMA request. Hardware may treat Bits 63:N as
reserved (0), where N is the maximum guest address
width (MGAW) supported. This field is relevant only when
the F field is set.
Reserved
0/0/0/VC0PREMAP
F00-F03h
00060000h
RW-L; RO
32 bits
(Sheet 1 of 3)
(Sheet 2 of 2)
Description
Processor Configuration Registers
Description
Datasheet