CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 108

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

108
21:20
19:18
Bit
25
24
23
22
Access
RW
RW
RW
RW
RW
RW
Default
Value
00b
00b
0b
0b
0b
0b
Refresh Counter Enable (REFCNTEN)
This bit is used to enable the refresh counter to count during
times that DRAM is not in self-refresh, but refreshes are not
enabled. Such a condition may occur due to need to
reprogram SO-DIMMs following DRAM controller switch.
This bit has no effect when Refresh is enabled (i.e. there is
no mode where Refresh is enabled but the counter does not
run) So, in conjunction with Bit 23 REFEN, the modes are:
All Rank Refresh (ALLRKREF)
This configuration bit enables (by default) that all the ranks
are refreshed in a staggered/atomic fashion. If set, the
ranks are refreshed in an independent fashion.
Refresh Enable (REFEN)
Refresh is enabled.
0 = Disabled
1 = Enabled
DDR Initialization Done (INITDONE)
Indicates that DDR initialization is complete.
DRAM Refresh Hysteresis (REFHYSTERISIS)
Hysteresis level - Useful for dref_high watermark cases. The
dref_high flag is set when the dref_high watermark level is
exceeded, and is cleared when the refresh count is less than
the hysteresis level. This bit should be set to a value less
than the high watermark level.
DRAM Refresh Panic Watermark (REFPANICWM)
When the refresh count exceeds this level, a refresh request
is launched to the scheduler and the dref_panic flag is set.
00: 3
01: 4
10: 5
11: 6
00: 5
01: 6
10: 7
11: 8
REFCNTEN
REFEN:
(Sheet 2 of 3)
0:0
0:1
1:X
Normal refresh disable
Refresh disabled, but
counter is accumulating
refreshes
Normal refresh enable
Processor Configuration Registers
Description
Description
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