CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 282

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.18.18
282
PHMLIMIT_REG - Protected High-Memory Limit Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to setup the limit address of DMA protected high-memory region. This register
must be setup before enabling protected memory through PMEN_REG, and must not be
updated when protected memory regions are enabled.
When LT.CMD.LOCK.PMRC command is invoked, this register is locked (treated RO).
When LT.CMD.UNLOCK.PMRC command is invoked, this register is unlocked (treated
RW).
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as 0 in the Capability register).
The alignment of the protected high memory region limit depends on the number of
reserved bits (N) of this register. Software may determine the value of N by writing all
1's to this register, and finding most significant zero bit position below host address
width (HAW) in the value read back from the register. Bits N:0 of the limit register is
decoded by hardware as all 1’s.
The protected high-memory base & limit registers functions as follows:- Programming
the protected low-memory base and limit registers with the same value in bits
HAW:(N+1) specifies a protected low-memory region of size 2
Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
63:21
20:0
Bit
Access
RW
RO
00000000
000000h
Default
Value
000h
Protected High-Memory Limit (PHML)
This register specifies the last host physical address of the
DMA protected high-memory region in system memory.
Hardware may not utilize Bits 63:HAW, where HAW is the
host address width.
Reserved
0/0/0/VC0PREMAP
78-7Fh
0000000000000000h
RO; RW
64 bits
Description
Processor Configuration Registers
(N+1)
bytes.-
Datasheet