CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 256

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

256
37:34
33:24
21:16
15:13
Bit
23
22
Access
RO
RO
RO
RO
RO
RO
100011b
Default
Value
0000b
020h
000b
0b
1b
Super Page Support (SPS)
This field indicates the super page sizes supported by
hardware.
A value of 1 in any of these bits indicates the corresponding
super-page size is supported. The super-page sizes
corresponding to various bit positions within this field are:
0: 21-bit offset to page frame
1: 30-bit offset to page frame
2: 39-bit offset to page frame
3: 48-bit offset to page frame
Fault-recording Register Offset (FRO)
This field specifies the location to the first fault recording
register relative to the register base address of this DMA-
remapping hardware unit.
If the register base address is X, and the value reported in this
field is Y, the address for the first fault recording register is
calculated as X+(16*Y).
Zero Length Read (ZLR)
0 = Indicates the remapping hardware unit blocks (and treats
1 = Indicates the remapping hardware unit supports zero
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability
supported by remapping hardware. The Maximum Guest
Address Width (MGAW) is computed as (N+1), where N is the
value reported in this field. For example, a hardware
implementation supporting 48-bit MGAW reports a value of 47
(101111b) in this field.
If the value in this field is X, DMA requests to addresses above
2
for a given DMA request is limited to the minimum of the
value reported through this field and the adjusted guest
address width of the corresponding page-table structure.
(Adjusted guest address widths supported by hardware are
reported through the SAGAW field).
Reserved
0 = Indicates this DMA-remapping hardware unit has no
1 = Indicates this DMA-remapping hardware unit has one or
Isochrony (Isoch)
(x+1)
as fault) zero length DMA read requests to write-only
pages.
length DMA read requests to write-only pages.
critical isochronous requesters in its scope.
more critical isochronous requesters in its scope. To
guarantee isochronous performance, software must
ensure invalidation operations do not impact active DMA
streams. This implies that when DMA is active, software
perform page-selective invalidations (instead of coarser
invalidations).
-1 are always blocked by hardware. Guest addressability
(Sheet 2 of 4)
Description
Processor Configuration Registers
Datasheet