CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 265

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.5
Datasheet
GSTS_REG - Global Status Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to report general DMA-remapping hardware status.
22:0
Bit
Bit
23
31
30
Access
Access
RO
RO
RO
W
000000h
Default
Default
Value
Value
0b
0b
0b
Compatibility Format Interrupt (CFI)
This field is valid only for Intel®64 implementations
supporting interrupt-remapping. Software writes to this field
to enable or disable Compatibility Format interrupts on
Intel®64 platforms. The value in this field is effective only
when interrupt-remapping is enabled and Legacy Interrupt
Mode is active.
0 = Block Compatibility format interrupts.
1 = Process Compatibility format interrupts as pass-through
Hardware reports the status of updating this field through the
CFIS field in the Global Status register. The value returned on
a read of this field is undefined.
This field is not implemented on Itanium® processor
implementations.
Reserved
Translation Enable Status (TES)
This field indicates the status of DMA-remapping hardware.
0 = DMA-remapping hardware is not enabled.
1 = DMA-remapping hardware is enabled.
Root Table Pointer Status (RTPS)
This field indicates the status of the root- table pointer in
hardware.
This field is cleared by hardware when software sets the SRTP
field in the Global Command register. This field is set by
hardware when hardware completes the set root-table pointer
operation using the value provided in the Root-Entry Table
Address register.
(bypass interrupt remapping).
0/0/0/VC0PREMAP
1C-1Fh
00000000h
RO
32 bits
(Sheet 5 of 5)
(Sheet 1 of 3)
Description
Description
265