CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 323

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.19.12
1.19.13
Datasheet
FEUADDR_REG - Fault Event Upper Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message upper address. This register is treated as
RsvdZ by implementations reporting Extended Interrupt Mode (EIM) as not supported
in the Extended Capability register.
AFLOG_REG - Advanced Fault Log Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to specify the base address of the memory-resident fault-log region. This
register is treated as RsvdZ for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register).
63:12
31:0
Bit
Bit
Access
Access
RO
RO
00000000
00000000
Default
Default
Value
00000h
Value
h
Message Upper Address (MUA)
Hardware implementations supporting Extended Interrupt
Mode are required to implement this register.
Software requirements for programming this register are
described in Intel VT-d specification Section 5.7.
Hardware implementations not supporting Extended
Interrupt Mode may treat this field as RsvdZ.
Fault Log Address (FLA)
This field specifies the base of 4-KB aligned fault-log region
in system memory. Hardware may ignore and not
implement Bits 63:HAW, where HAW is the host address
width.
Software specifies the base address and size of the fault log
region through this register, and programs it in hardware
through the SFL field in the Global Command register.
When implemented, reads of this field returns value that
was last programmed to it.
0/0/0/DMIVC1REMAP
44-47h
00000000h
RO
32 bits
0/0/0/DMIVC1REMAP
58-5Fh
0000000000000000h
RO
64 bits
(Sheet 1 of 2)
Description
Description
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