CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 120

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.10.6
120
TSTTPA1 - Thermal Sensor Temperature Trip Point A1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register:
1. Sets the target values for some of the trip points in thermometer mode. See also
2. Reports the relative thermal sensor temperature See also TSTTPB.
29:16
15:8
7:0
Bit
31
30
TST [Direct DAC Connect Test Enable].
Access
RW-L
RW-L
RW-L
RW-L
RO
Default
Value
0000h
00h
00h
0b
0b
Lock Bit for Aux0, Aux1, Aux2 and Aux3 Trip Points
(AUXLOCK)
This bit, when written to a 1, locks the Aux x Trip point
settings.
It is expected that the Aux x Trip point settings can be
changed dynamically when this lock is not set.
Lock Bit for Catastrophic (LBC)
This bit, when written to a 1, locks the Catastrophic
programming interface, including Bits 7:0 of TSTTPA[15-0],
Bits 15 and 9 of TSC, and Bits 10 and 8 of TST1. This bit may
only be set to a 0 by a hardware reset. Writing a 0 to this bit
has no effect.
Reserved
Hot Trip Point Setting (HTPS)
Sets the target value for the Hot trip point. Lockable via
TSTTPA1 Bit 30.
Catastrophic Trip Point Setting (CTPS)
Sets the target for the Catastrophic trip point. See also
TST[Direct DAC Connect Test Enable]. Lockable via TSTTPA1
Bit 30.
0/0/0/MCHBAR
1010-1013h
00000000h
RW-L; RO
32 bits
Processor Configuration Registers
Description
Datasheet