CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 179

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.13.36
Datasheet
DCTL - Device Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Provides control for PCI Express device specific capabilities.
The error reporting enable bits are in reference to errors detected by this device, not
error messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by Root
Port Command Register.
14:12
7:5
Bit
15
11
10
9
8
4
3
2
Access
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
Default
Value
000b
000b
0h
0b
0b
0b
0b
0b
0b
0b
Reserved
Reserved for Max Read Request Size (MRRS)
Reserved for Enable No Snoop (RSVD)
Reserved
Reserved for Auxiliary (AUX) PM Enable ()
Reserved
Reserved for Phantom Functions Enable ()
Reserved
Reserved for Extended Tag Field Enable ()
Max Payload Size (MPS)
000:128B max supported payload for Transaction Layer
Packets (TLP). As a receiver, the Device must handle TLPs as
large as the set value; as transmitter, the Device must not
generate TLPs exceeding the set value.
All other encodings are reserved.
Hardware will actually ignore this field. It is writeable only to
support compliance testing.
Reserved for Enable Relaxed Ordering (RSVD)
Unsupported Request Reporting Enable (URRE)
When set, allows signaling ERR_NONFATAL, ERR_FATAL, or
ERR_CORR to the Root Control register when detecting an
unmasked Unsupported Request (UR). An ERR_CORR is
signaled when an unmasked Advisory Non-Fatal UR is
received. An ERR_FATAL or ERR_NONFATAL is sent to the Root
Control register when an uncorrectable non-Advisory UR is
received with the severity bit set in the Uncorrectable Error
Severity register.
Fatal Error Reporting Enable (FERE)
When set, enables signaling of ERR_FATAL to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope
of related error reporting.
0/1/0/PCI
A8-A9h
0000h
RO; RW
16 bits
(Sheet 1 of 2)
Description
179