CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 234
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 234 of 388
- Download datasheet (2Mb)
1.16.13
1.16.14
234
SVID2 - Subsystem Vendor Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
SID2 - Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
31:16
15:3
15:0
15:0
2:1
Bit
Bit
Bit
0
Access
Access
Access
RW-O
RW-O
RW
RO
RO
RO
Default
Default
Default
Value
0000h
Value
0000h
0000h
0000h
Value
00b
1b
FLR, Core
RST/
RST/
PWR
PWR
Core
Core
RST/
PWR
Core
Core
Core
0/2/0/PCI
2C-2Dh
0000h
RW-O
16 bits
0/2/0/PCI
2E-2Fh
0000h
RW-O
16 bits
Subsystem Vendor ID (SUBVID)
This value is used to identify the vendor of the
subsystem. This register should be programmed
by BIOS during boot-up. Once written, this
register becomes Read_Only. This register can
only be cleared by a Reset.
Subsystem Identification (SUBID)
This value is used to identify a particular
subsystem. This field should be programmed by
BIOS during boot-up. Once written, this register
becomes Read_Only. This register can only be
cleared by a Reset.
Reserved
IO Base Address (IOBASE)
Set by the OS, these bits correspond to address
signals [15:3].
Memory Type (MEMTYPE)
Memory/IO Space (MIOS)
hard wired to 0’s to indicate 32-bit address.
hard wired to 1 to indicate IO space.
Processor Configuration Registers
Description
Description
Description
Datasheet
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