CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 37

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.2.8
1.2.9
Datasheet
SMM and VGA Access through GTT TLB
Accesses through GTT TLB address translation SMM DRAM space are not allowed.
Writes is routed to Memory address 000C_0000h with byte enables de-asserted and
reads is routed to Memory address 000C_0000h. If a GTT TLB translated address hits
SMM DRAM space, an error is recorded in the PGTBL_ER register.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded in the PGTBL_ER register.
PCI Express and DMI Interface write accesses through GMADR range will not be
snooped. Only PCI Express and DMI assesses to GMADR linear range (defined via fence
registers) are supported. PCI Express and DMI Interface tileY and tileX writes to
GMADR are not supported. If, when translated, the resulting physical address is to
enabled SMM DRAM space, the request is remapped to address 000C_0000h with de-
asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported,
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR is remapped to address 000C_0000h. The read will complete with UR
(unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure they are not in SMM (actually,
to ensure they are not above base of TSEG or 640 K -1 M. Thus, they are invalid and go
to address 000C_0000h, but that isn’t specific to PCI Express or DMI; it applies to CPU
or internal graphics engines.
I/O Address Space
The GMCH generates either DMI Interface or PCI Express bus cycles for all CPU I/O
accesses that it does not claim. The GMCH no longer contains the two internal registers
in the CPU I/O space, Configuration Address Register (CONFIG_ADDRESS) and the
Configuration Data Register (CONFIG_DATA).
The CPU allows 64K+3 bytes to be addressed within the I/O space. The GMCH
propagates the CPU I/O address without any translation on to the destination bus and
therefore provides addressability for 64K+3 byte locations. Note that the upper 3
locations can be accessed only during I/O address wrap-around when Address Bit 16 is
asserted. Address Bit 16 is asserted on the CPU bus whenever an I/O access is made to
4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. Address Bit 16 is also asserted when
an I/O access is made to 2 bytes from address 0FFFFh.
A set of I/O accesses are consumed by the internal graphics device if it is enabled. The
mechanisms for internal graphics IO decode and the associated control is explained
later.
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