CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 15

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
When running in internal graphics mode, tileX/tileY/linear reads/writes to GMADR
range are supported. Write accesses to GMADR linear regions are supported from both
DMI and PEG. GMADR write accesses to tileX and tileY regions (defined via fence
registers) are not supported from DMI or the PEG port. GMADR read accesses are not
supported from either DMI or PEG.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI Interface. The exception to this rule is VGA ranges, which may be
mapped to PCI Express*, DMI, or to the internal graphics device (IGD). In the absence
of more specific references, cycle descriptions referencing PCI should be interpreted as
the DMI Interface/PCI, while cycle descriptions referencing PCI Express or IGD are
related to the PCI Express bus or the internal graphics device, respectively. The GMCH
does not remap APIC or any other memory spaces above TOLUD (Top of Low Usable
DRAM). The TOLUD register is set to the appropriate value by BIOS. The remapbase/
remaplimit registers remap logical accesses bound for addresses above 4 GB onto
physical addresses that fall within DRAM.
Figure 1
represents system memory address map in a simplified form.
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