CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 240

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

240
7:4
3:2
Bit
1
0
Access
RO
RO
RO
RO
Default
Value
0011b
00b
0b
0b
Graphics Mode Select (GMS)
This field is used to select the amount of Main Memory that
is pre-allocated to support the Internal Graphics device in
VGA (non-linear) and Native (linear) modes. The BIOS
ensures that memory is pre-allocated only when Internal
graphics is enabled.
0000: No memory pre-allocated. Device 2 (IGD) does not
claim VGA cycles (Mem and IO), and the Sub-Class Code
field within Device 2 function 0 Class Code register is 80.
Defined values: DVMT (UMA) mode, memory pre-allocated
for frame buffer, in quantities as shown in the Encoding
table. Values larger than 128 MB include 128 MB for
Protected Content Memory.
Encoding Description
0h No memory pre-allocate
5h 32 MB
7h 64 MB
8h 128 MB
Bh 160 MB
Ch 224 MB
Dh 352 MB
NOTE: This register is locked and becomes Read Only when
BIOS Requirement: BIOS must not set this field to 000 if
IVD (Bit 1 of this register) is 0.
Reserved
IGD VGA Disable (IVD)
Enable. Device 2 (IGD) claims VGA memory and IO cycles,
the Sub-Class Code within Device 2 Class Code register is
00.
Disable. Device 2 (IGD) does not claim VGA cycles (Mem and
IO), and the Sub- Class Code field within Device 2 Function 0
Class Code register is 80.
BIOS Requirement: BIOS must not set this bit to 0 if the
GMS field (Bits 6:4 of this register) pre-allocates no memory.
This bit MUST be set to 1 if Device 2 is disabled via register
(DEVEN[3] = 0).
Reserved
(Sheet 2 of 2)
the D_LCK bit in the SMRAM register is set.
Processor Configuration Registers
Description
Datasheet