CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 23

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.2.2.6.3
1.2.2.7
1.2.2.8
Datasheet
Note:
Note:
Direct accesses to GGSM are not allowed, only hardware translations and fetches can
be directed to GGSM.
Shadow GTT Stolen Space (SGSM)
Shadow GSM is only used once internal GFX and Intel VT-d translations are enabled.
The purpose of shadow GSM is to provide a physical space to hardware, where Intel
VT-d translation for PTE updates can be made on the fly and re-written back into
physical memory.
Intel® Management Engine (Intel® ME) UMA
Intel ME can be allocated UMA memory. The Intel ME memory is “stolen” from the top
of the Host address map. Intel ME stolen memory base is calculated by subtracting the
amount of memory stolen by the Manageability Engine from TOM.
Only Intel ME can access this space; it is not accessible by or coherent with any CPU
side accesses.
PCI Memory Address Range (TOLUD - 4 GB)
This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
Device 0 exceptions are:
For each PCI Express port, there are two exceptions to this rule.
In integrated graphics configurations, there are exceptions to this rule:
1. Addresses decoded to the egress port registers (PXPEPBAR)
2. Addresses decoded to the memory mapped range for internal GMCH registers
3. Addresses decoded to the registers associated with the GMCH/PCH Serial
1. Addresses decoded to the PCI Express Memory Window defined by the MBASE1,
2. Addresses decoded to the PCI Express prefetchable Memory Window defined by the
1. Addresses decode to the internal graphics translation window (GMADR)
2. Addresses decode to the Internal graphics translation table or IGD registers.
(GMCHBAR)
Interconnect (DMI) register memory range. (DMIBAR)
MLIMIT1, registers are mapped to PCI Express.
PMBASE1, PMLIMIT1, registers are mapped to PCI Express.
(GTTMMADR)
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