CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 322

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.10
1.19.11
322
FEDATA_REG - Fault Event Data Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message data.
FEADDR_REG - Fault Event Address Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register specifying the interrupt message address.
31:16
15:0
31:2
1:0
Bit
Bit
Access
Access
RW
RW
RO
RO
00000000
Default
Default
Value
0000h
0000h
Value
00b
h
Extended Interrupt Message Data (EIMD)
This field is valid only for implementations supporting 32-bit
MSI data fields. Hardware implementations supporting only
16-bit MSI data may treat this field as read-only (0).
Interrupt message Data (ID)
Data value in the interrupt request. Software requirements
for programming this register are described in Intel VT-d
specification Section 5.7.
Message Address (MA)
When fault events are enabled, the contents of this register
specify the DWORD aligned address (Bits 31:2) for the
interrupt request.
Software requirements for programming this register are
described in Intel VT-d specification Section 5.7.
Reserved
0/0/0/DMIVC1REMAP
3C-3Fh
00000000h
RO; RW
32 bits
0/0/0/DMIVC1REMAP
40-43h
00000000h
RO; RW
32 bits
Processor Configuration Registers
Description
Description
Datasheet