CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 123

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.9
Datasheet
TIS1 - Thermal Interrupt Status 1
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register is used to report which specific error condition resulted in the D2F0 or
D2F1 ERRSTS [Thermal Sensor event for SMI/SCI/SERR] or memory mapped IIR
Thermal Event. SW can examine the current state of the thermal zones by examining
the TSS. Software can distinguish internal or external Trip Event by examining TSS.
15:14
Bit
10
13
12
11
9
Access
RWC
RWC
RWC
RWC
RWC
RO
Default
Value
00b
0b
0b
0b
0b
0b
Reserved
Was Catastrophic Thermal Sensor Interrupt Event
(WCTSIE)
0 = No trip for this event.
1 = Indicates that a Catastrophic Thermal Sensor trip based
Software must write a 1 to clear this status bit.
Was Hot Thermal Sensor Interrupt Event (WHTSIE)
0 = No trip for this event.
1 = A Hot Thermal Sensor trip occurred based on a higher to
Software must write a 1 to clear this status bit.
Was Aux 3 Thermal Sensor Interrupt Event
(WA3TSIE)
0 = No trip for this event.
1 = An Aux3 Thermal Sensor trip occurred based on a higher
Software must write a 1 to clear this status bit.
Was Aux 2 Thermal Sensor Interrupt Event
(WA2TSIE)
0 = No trip for this event.
1 = An Aux2 Thermal Sensor trip occurred based on a higher
Software must write a 1 to clear this status bit.
Was Aux 1 Thermal Sensor Interrupt Event
(WA1TSIE)
0 = No trip for this event.
1 = An Aux1 Thermal Sensor trip occurred based on a higher
Software must write a 1 to clear this status bit.
0/0/0/MCHBAR
101E-101Fh
0000h
RO; RWC
16 bits
on a higher to lower temperature transition thru the trip
point.
lower temperature transition through the trip point.
to lower temperature transition through the trip point.
to lower temperature transition through the trip point.
to lower temperature transition through the trip point.
(Sheet 1 of 3)
Description
123