CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 172

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

172
1:0
Bit
Access
RW
Default
Value
00b
Power State (PS)
Indicates the current power state of this device and can be
used to set the device into a new power state. If software
attempts to write an unsupported state to this field, write
operation must complete normally on the bus, but the data is
discarded and no state change occurs.
00:
01:
10:
11:
Support of D3cold does not require any special action. While
in the D3hot state, this device can only act as the target of
PCI configuration transactions (for power management
control).
This device also cannot generate interrupts or respond to
MMR cycles in the D3 state. The device must return to the D0
state in order to be fully-functional.
When the Power State is other than D0, the bridge will Master
Abort (i.e., not claim) any downstream cycles (with exception
of type 0 config cycles).
Consequently, these unclaimed cycles will go down DMI and
come back up as Unsupported Requests, which the
PROCESSOR logs as Master Aborts in Device 0 PCISTS[13]
There is no additional hardware functionality required to
support these Power States.
D0
D1 (Not supported in this device.)
D2 (Not supported in this device.)
D3
(Sheet 2 of 2)
Processor Configuration Registers
Description
Datasheet