CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 194

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

194
Bit
7
6
5
4
Access
RO
RO
RO
RO
Default
Value
0b
0b
0b
0b
Reserved for Electromechanical Interlock Status (EIS)
If an Electromechanical Interlock is implemented, this bit
indicates the current status of the Electromechanical
Interlock.
Defined encodings are:
0b Electromechanical Interlock Disengaged
1b Electromechanical Interlock Engaged
Presence Detect State (PDS)
In band presence detect state:
0b: Slot Empty
1b: Card present in slot
This bit indicates the presence of an adapter in the slot,
reflected by the logical “OR” of the Physical Layer in-band
presence detect mechanism and, if present, any out-of-band
presence detect mechanism defined for the slot's
corresponding form factor. Note that the in-band presence
detect mechanism requires that power be applied to an
adapter for its presence to be detected. Consequently, form
factors that require a power controller for hot-plug must
implement a physical pin presence detect mechanism.
Defined encodings are:
0b Slot Empty
1b Card Present in slot
This register must be implemented on all Downstream Ports
that implement slots. For Downstream Ports not connected to
slots (where the Slot Implemented bit of the PCI Express
Capabilities Register is 0b), this bit must return 1b.
Reserved for MRL Sensor State (MSS)
This register reports the status of the MRL sensor if it is
implemented.
Defined encodings are:
0b MRL Closed
1b MRL Open
Reserved for Command Completed (CC)
If Command Completed notification is supported (as indicated
by No Command Completed Support field of Slot Capabilities
Register), this bit is set when a hot-plug command has
completed and the Hot-Plug Controller is ready to accept a
subsequent command. The Command Completed status bit is
set as an indication to host software that the Hot-Plug
Controller has processed the previous command and is ready
to receive the next command; it provides no guarantee that
the action corresponding to the command is complete.
If Command Completed notification is not supported, this bit
must be hard wired to 0b.
(Sheet 2 of 3)
Processor Configuration Registers
Description
Datasheet