CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 13

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
Datasheet
RW1C-L-S
RW1C-S
RW-K
RW-L
RW-L-K
RW-V
RW-V-L
RW-V-L-S
RW-S
Item
Read/Write 1 to Clear/Lockable/Sticky bit(s). These bits can be read.
Internal events may set this bit. A software write of 1 clears (sets to 0) the
corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
“warm” reset, but is reset with a cold/complete reset (for PCI Express related
bits a cold reset is “Power Good Reset” as defined in the PCI Express Base
spec). Additionally there is a Key bit (which is marked RW-K or RW-L-K) that,
when set, prohibits this bit field from being writable (bit field becomes Read
Only/Volatile).
Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal
events may set this bit. A software write of 1 clears (sets to 0) the
corresponding bit(s) and a write of 0 has no effect. Bits are not cleared by
"warm" reset, but is reset with a cold/complete reset (for PCI Express related
bits a cold reset is “Power Good Reset” as defined in the PCI Express Base
spec).
Read/Write/Key bit(s). These bits can be read and written by software.
Additionally this bit, when set, prohibits some other target bit field from being
writable (bit fields become Read Only).
Read/Write/Lockable bit(s). These bits can be read and written by
software. Additionally there is a Key bit (which is marked RW-K or RW-L-K)
that, when set, prohibits this bit field from being writable (bit field becomes
Read Only).
Read/Write/Lockable/Key bit(s). These bits can be read and written by
software. This bit, when set, prohibits some other bit field(s) from being
writable (bit fields become Read Only). Additionally there is a Key bit (which is
marked RW-K or RW-L-K) that, when set, prohibits this bit field from being
writable (bit field becomes Read Only).
Conceptually, this may be a cascaded lock, or it may be self-locking when in
its non-default state. When self-locking, it differs from RW-O in that writing
back the default value will not set the lock.
Write/Volatile bit(s). These bits can be read and written by software.
Hardware may set or clear the bit based on internal events, possibly sooner
than any subsequent software read could retrieve the value written.
Read/Write/Volatile/Lockable bit(s). These bits can be read and written
by software. Hardware may set or clear the bit based upon internal events,
possibly sooner than any subsequent software read could retrieve the value
written Additionally there is a bit (which is marked RW-K or RW-L-K) that,
when set, prohibits this bit field from being writable (bit field becomes Read
Only).
Read/Write/Volatile/Lockable/Sticky bit(s). These bits can be read and
written by software. Hardware may set or clear the bit based upon internal
events, possibly sooner than any subsequent software read could retrieve the
value written Additionally there is a bit (which is marked RW-K or RW-L-K)
that, when set, prohibits this bit field from being writable (bit field becomes
Read Only). These bits return to their default values on cold reset.
Read/Write/Sticky bit(s). These bits can be read and written by software.
Bits are not returned to their default values by “warm” reset, but will return to
default values with a cold/complete reset (for PCI Express related bits a cold
reset is “Power Good Reset” as defined in the PCI Express spec).
(Sheet 2 of 3)
Description
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