CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 95

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.15
Datasheet
C0CKECTRL - Channel 0 CKE Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
CKE controls for Channel 0.
31:28
26:24
19:17
16:14
Bit
27
23
22
21
20
Access
RW-L
RW-L
RW-L
RW-L
RW
RW
RW
RO
RO
Default
Value
000b
000b
000b
0h
0b
0b
0b
0b
0b
Reserved
Start the Self-refresh Exit Sequence (sd0_cr_srcstart)
This configuration register indicates the request to start the
self-refresh exit sequence.
CKE Pulse Width Requirement in High Phase
(sd0_cr_cke_pw_hl_safe)
This configuration register indicates CKE pulse width
requirement in high phase.
Corresponds to the tCKE (high) parameter in the DDR3
specification.
Rank 3 Population (sd0_cr_rankpop3)
This register is locked by Intel ME stolen Memory lock.
Rank 2 Population (sd0_cr_rankpop2)
This register is locked by Intel ME stolen Memory lock.
Rank 1 Population (sd0_cr_rankpop1)
This register is locked by Intel ME stolen Memory lock.
Rank 0 Population (sd0_cr_rankpop0)
This register is locked by Intel ME stolen Memory lock.
CKE Pulse Width Requirement in Low Phase
(sd0_cr_cke_pw_lh_safe)
This configuration register indicates CKE pulse width
requirement in low phase.
Corresponds to the tCKE (low) parameter in the DDR3
specification.
Reserved
1: Rank 3 populated.
0: Rank 3 not populated.
1: Rank 2 populated.
0: Rank 2 not populated.
1: Rank 1 populated.
0: Rank 1 not populated.
1: Rank 0 populated.
0: Rank 0 not populated.
0/0/0/MCHBAR
260-263h
000009FEh
32 bits
RW-L; RO; RW
(Sheet 1 of 2)
Description
95