CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 237

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.20
1.16.21
Datasheet
MAXLAT - Maximum Latency
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
GGCTL - Graphics Enhanced Intel® SpeedStep Technology
Capability
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register conveys the maximum frequencies and voltages supported by this
particular component, as determined by manufacturing testing. This information is
intended to be used by software to properly configure the graphics clocking solution.
Hardware does not directly use this information or enforce these limits in any way.
30:24
23:22
21:16
7:0
Bit
Bit
31
15
Access
Access
RO
RO
RO
RO
RO
RO
Default
Default
Value
Value
00h
00b
00h
3Fh
0b
0b
Maximum Latency Value (MLV)
The IGD has no specific requirements for how
often it needs to access the PCI bus.
Reserved
Max Turbo Graphics Render Voltage ID (MTGRVID)
The voltage required to operate at the Maximum Turbo
Graphics Render Frequency.
The encoding of this field follows the definition of the Intel®
MVP 6.5 Voltage Regulator, which is:
Example: 0100000b = 1.1 V
Reserved
Max Turbo Graphics Render Frequency (MTGRF)
The maximum frequency at which the graphics render clock
may operate under “Turbo” conditions, which may exceed
specified TDP budget of the processor. This field is a binary
encoding of the maximum frequency divided by 33.333 MHz.
Example: 011000b = 800 MHz
Reserved
Voltage = 1.5 V - <field> * 0.0125 V (min of 0 V)
Max Frequency = <field> * 33.333 MHz
0/2/0/PCI
3Fh
00h
RO
8 bits
0/2/0/PCI
4C-4Fh
003F003Fh
RO
32 bits
(Sheet 1 of 2)
Description
Description
237