CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 107

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.31
Datasheet
C1REFRCTRL - Channel 1 DRAM Refresh Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Settings to configure the DRAM refresh controller.
46:44
43:38
37:32
31:27
13:10
9:1
Bit
Bit
47
26
0
Access
Access
RW
RW
RW
RW
RW
RW
RW
RW
RO
00000000
Default
Default
00110b
Value
Value
0010b
010b
10h
18h
0b
0b
0b
0b
Reserved
Initial Refresh Count (INITREFCNT)
Specifies Initial Refresh Count Value
Direct Rcomp Quiet Window (DIRQUIET)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
Indirect Rcomp Quiet Window (INDIRQUIET)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
Rcomp Wait (RCOMPWAIT)
This configuration setting indicates the amount of
refresh_tick events to wait before the service of Rcomp
request in non-default mode of independent rank refresh.
Reserved
Minimum Powerdown Exit to Non-Read command
spacing (sd1_cr_txp)
This configuration register indicates the minimum number of
clocks to wait following assertion of CKE before issuing a
non-read command.
1010-1111=Reserved
0010-1001=2-9 clocks
0000-0001=Reserved.
Self Refresh Exit Count (sd1_cr_slfrfsh_exit_cnt)
This configuration register indicates the Self refresh exit
count. (Program to 255)
Corresponds to tXSNR/tXSRD at DDR Spec.
Indicates only 1 SO-DIMM populated
(sd1_cr_singledimmpop)
This configuration register indicates that only 1 SO_DIMM is
populated.
0/0/0/MCHBAR
669-66Eh
241830000C30h
RO; RW
48 bits
(Sheet 1 of 3)
(Sheet 2 of 2)
Description
Description
107