CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 283

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.18.19
1.18.20
Datasheet
IQH_REG - Invalidation Queue Head Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register indicating the invalidation queue head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
IQT_REG - Invalidation Queue Tail Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register indicating the invalidation queue tail. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
63:19
63:19
18:4
18:4
3:0
3:0
Bit
Bit
Access
Access
RO
RO
RO
RO
RO
RO
00000000
00000000
Default
Default
Value
0000h
0000h
Value
0000h
0000h
0h
0h
Reserved
Queue Head (QH)
Specifies the offset (128-bit aligned) to the invalidation
queue for the command that is fetched next by hardware.
Hardware resets this field to 0 whenever the queued
invalidation is disabled (QIES field Clear in the Global Status
register).
Reserved
Reserved
Queue Tail (QT)
Specifies the offset (128-bit aligned) to the invalidation
queue for the command that is written next by software.
Reserved
0/0/0/VC0PREMAP
80-87h
0000000000000000h
RO
64 bits
0/0/0/VC0PREMAP
88-8Fh
0000000000000000h
RO
64 bits
Description
Description
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