CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 360

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.20.7
360
CCMD_REG - Context Command Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to manage context cache. The act of writing the uppermost byte of the
CCMD_REG with the ICC field set causes the hardware to perform the context-cache
invalidation.
Bit
63
Access
RW
Default
Value
0b
Invalidate Context Cache (ICC)
Software requests invalidation of context-cache by setting
this field. Software must also set the requested invalidation
granularity by programming the CIRG field. Software must
read back and check the ICC field is Clear to confirm the
invalidation is complete. Software must not update this
register when this field is Set.
Hardware clears the ICC field to indicate the invalidation
request is complete. Hardware also indicates the granularity
at which the invalidation operation was performed through
the CAIG field.
Software must submit a context-cache invalidation request
through this field only when there are no invalidation
requests pending at this remapping hardware unit.
Since information from the context-cache may be used by
hardware to tag IOTLB entries, software must perform
domain-selective (or global) invalidation of IOTLB after the
context cache invalidation has completed.
Hardware implementations reporting a write-buffer flushing
requirement (RWBF=1 in the Capability register) must
implicitly perform a write buffer flush before invalidating the
context-cache..
0/2/0/GFXVTBAR
28-2Fh
0800000000000000h
RO; RW
64 bits
(Sheet 1 of 3)
Processor Configuration Registers
Description
Datasheet