CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 180

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.37
180
DSTS - Device Status
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Reflects status corresponding to controls in the Device Control register. The error
reporting bits are in reference to errors detected by this device, not errors messages
received across the link.
15:6
Bit
Bit
1
0
5
4
3
Access
Access
RW
RW
RWC
RO
RO
RO
Default
Value
0b
0b
Default
Value
000h
0b
0b
0b
Non-Fatal Error Reporting Enable (NERE)
When set, enables signaling of ERR_NONFATAL to the Root
Control register due to internally detected errors or error
messages received across the link. Other bits also control the
full scope of related error reporting.
Correctable Error Reporting Enable (CERE)
When set, enables signaling of ERR_CORR to the Root Control
register due to internally detected errors or error messages
received across the link. Other bits also control the full scope
of related error reporting.
Reserved and Zero (RSVD)
For future R/WC/S implementations; software must use
0 for writes to bits.
Transactions Pending (TP)
0 = All pending transactions (including completions for
1 = Indicates that the device has transaction(s) pending
Unsupported Request Detected (URD)
When set this bit indicates that the Device received an
Unsupported Request. Errors are logged in this register
regardless of whether error reporting is enabled or not in
the Device Control Register.
Additionally, the Non-Fatal Error Detected bit or the Fatal
Error Detected bit is set according to the setting of the
Unsupported Request Error Severity bit. In production
systems setting the Fatal Error Detected bit is not an
option as support for AER will not be reported.
0/1/0/PCI
AA-ABh
0000h
RO; RWC
16 bits
Reserved
(Sheet 2 of 2)
(Sheet 1 of 2)
any outstanding non-posted requests on any used
virtual channel) have been completed.
(including completions for any outstanding non-
posted requests for all used Traffic Classes).
Processor Configuration Registers
Description
Description
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