CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 112

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.34
112
C1DTPEW - Channel 1 DRAM Rank Throttling Passive Event
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Programmable Event weights are input into the averaging filter. Each Event weight is an
normalized 8-bit value that the BIOS must program. The BIOS must account for burst
length and 1N/2N rule considerations. It is also possible for BIOS to take into account
loading variations of memory caused as a function of memory types and population of
ranks. GMCH implements 4 independent filters, one per rank. All bits in this register
can be locked by the DTLOCK bit in the C1DTC register.
31:24
23:16
15:8
7:0
Bit
Access
RW-L
RW-L
RW-L
RW-L
Default
Value
00h
00h
00h
00h
0/0/0/MCHBAR
6A8-6ABh
00000000h
32 bits
RW-L
Reserved
Reserved
Reserved
Reserved
Description
Processor Configuration Registers
Datasheet