CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 89

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.9.10
Datasheet
C0CYCTRKACT - Channel 0 CYCTRK ACT
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK Activate Registers.
31:28
27:22
20:17
16:13
12:9
8:0
Bit
21
Access
RW
RW
RW
RW
RW
RW
RO
Default
Value
000h
00b
00h
0b
0h
0h
0h
Reserved
Activate Window Count (C0sd_cr_act_windowcnt)
This configuration register indicates the window duration (in
DRAM clocks) during which the controller counts the number
of activate commands which are launched to a particular
rank. If the number of activate commands launched within
this window is greater than 4, then a check is implemented to
block launch of further activates to this rank for the rest of
the duration of this window.
Max Activate Check (C0sd_cr_maxact_dischk)
This configuration register enables the check which ensures
that there are no more than four activates to a particular rank
in a given window.
Activate to Activate Delay (C0sd_cr_act_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two ACT commands to the
same rank.
Corresponds to the tRRD parameter in the DDR3
Specification.
Precharge to Activate Delay (C0sd_cr_pre_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the PRE and ACT
commands to the same rank-bank.
Corresponds to the tRP parameter in the DDR3 Specification.
Precharge All to Activate Delay (C0sd_cr_preall_act)
From the launch of a precharge-all command wait for this
many memory bus clocks before launching an activate
command.
Corresponds to the tPALL_RP parameter.
Refresh to Activate Delay (C0sd_cr_rfsh_act)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between REF and ACT commands to
the same rank.
Corresponds to the tRFC parameter in the DDR3
Specification.
0/0/0/MCHBAR
252-255h
00000000h
RO; RW
32 bits
Description
89