CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 90

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.9.11
90
C0CYCTRKWR - Channel 0 CYCTRK WR
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Channel 0 CYCTRK WR Registers.
15:12
11:8
7:4
3:0
Bit
Access
RW
RW
RW
RW
Default
Value
0h
0h
0h
0h
Activate-to-Write Delay (C0sd_cr_act_wr) This
configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the ACT and WRITE
commands to the same rank-bank.
Corresponds to the tRCD_wr parameter DDR3 specification.
Same Rank Write-to-Write Delay (C0sd_cr_wrsr_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands to
the same rank.
Different Rank Write-to-Write Delay
(C0sd_cr_wrdr_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between two WRITE commands to
different ranks.
Corresponds to the tWR_WR parameter in the DDR3
specification.
Read-to-Write Delay (C0sd_cr_rd_wr)
This configuration register indicates the minimum allowed
spacing (in DRAM clocks) between the READ and WRITE
commands.
Corresponds to the tRD_WR parameter.
0/0/0/MCHBAR
256-257h
0000h
RW
16 bits
Processor Configuration Registers
Description
Datasheet