CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 168

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.24
168
BCTRL1 - Bridge Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register provides extensions to the PCICMD1 register that are specific to PCI-PCI
bridges. The BCTRL provides additional control for the secondary interface (i.e., PCI
Express-G) as well as some bits that affect the overall behavior of the “virtual” Host-
PCI Express bridge embedded within processor, e.g., VGA compatible address ranges
mapping.
15:12
Bit
11
10
9
8
7
6
5
4
Access
RW
RW
RO
RO
RO
RO
RO
RO
RO
Default
Value
0h
0b
0b
0b
0b
0b
0b
0b
0b
Reserved
Discard Timer SERR# Enable (DTSERRE)
Not Applicable or Implemented. Hard wired to 0.
Discard Timer Status (DTSTS)
Not Applicable or Implemented. Hard wired to 0.
Secondary Discard Timer (SDT)
Not Applicable or Implemented. Hard wired to 0.
Primary Discard Timer (PDT)
Not Applicable or Implemented. Hard wired to 0.
Fast Back-to-Back Enable (FB2BEN)
Not Applicable or Implemented. Hard wired to 0.
Secondary Bus Reset (SRESET)
Setting this bit triggers a hot reset on the corresponding PCI
Express Port. This will force the LTSSM to transition to the Hot
Reset state (via Recovery) from L0, L0s, or L1 states.
Master Abort Mode (MAMODE)
Does not apply to PCI Express. Hard wired to 0.
VGA 16-bit Decode (VGA16D)
Enables the PCI-to-PCI bridge to provide 16-bit decoding of
VGA I/O address precluding the decoding of alias addresses
every 1 KB. This bit only has meaning if Bit 3 (VGA Enable) of
this register is also set to 1, enabling VGA I/O decoding and
forwarding by the bridge.
0 = Execute 10-bit address decodes on VGA I/O accesses.
1 = Execute 16-bit address decodes on VGA I/O accesses.
0/1/0/PCI
3E-3Fh
0000h
RO; RW
16 bits
(Sheet 1 of 2)
Description
Processor Configuration Registers
Datasheet