CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 324

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.19.14
324
PMEN_REG - Protected Memory Enable Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Register to enable the DMA-protected memory regions set up through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is treated as RO for
implementations not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).
Protected memory regions may be used by software to securely initialize remapping
structures in memory.
11:9
8:0
Bit
Access
RO
RO
Default
Value
000b
000h
Fault Log Size (FLS)
This field specifies the size of the fault log region pointed by
the FLA field. The size of the fault log region is (2^X) * 4
KB, where X is the value programmed in this register.
When implemented, reads of this field returns value that
was last programmed to it.
Reserved
000: 4 KB
001: 8 KB
010: 16 KB
011: 32 KB
100: 64 KB
101: 128 KB
110: 256 KB
111: 512 KB
0/0/0/DMIVC1REMAP
64-67h
00000000h
RO; RW
32 bits
(Sheet 2 of 2)
Processor Configuration Registers
Description
Datasheet