CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 387

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.21.2
Datasheet
TXT.DPR - DMA Protected Range
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
DMA protected range register.
47:32
31:16
63:32
31:20
19:12
15:0
11:4
Bit
3:1
Bit
0
Access
Access
RW-L-K
RW-L
RO
RO
RO
RO
RO
RO
RO
Default
Default
000000
A000h
Value
000Fh
8086h
Value
000h
000b
00h
00h
00h
0b
Revision ID (TXT.RID)
For the initial stepping of the component, the value is 0001h.
The value is a bit-mask for compatibility with prior steppings.
For the B-0 stepping, this value is 0003h.
For the C-0 stepping, this value is 0007h.
For the C-2 stepping this value is 000Fh
Device ID (TXT.DID)
0xA000
Vendor ID (TXT.VID)
This register field contains the PCI standard identification for
Intel, 8086h.
Reserved
Top of DMA Protected Range (TopOfDPR)
Top address + 1 of DPR. This is the base of TSEG. Bits 19:0 of
the BASE reported here are 0x0_0000.
Reserved
DMA Protected Memory Size (DPR.SIZE)
This is the size of memory, in MB, that will be protected from
DMA accesses. A value of 0x00 in this field means no additional
memory is protected. The maximum amount of memory that
will be protected is 255 MB.
Reserved
Lock (LOCK)
Bits 19:0 are locked down in this register when this bit is set.
This bit is a write-once bit. If BIOS writes a ‘0’ to the bit, then it
can not be written to a ‘1’ on subsequent writes. BIOS must
write the entire register with the correct values and set this bit
with that write.
0/0/0/TXT Specific
330-337h
0000000000000000h
64 bits
RO; RW-L; RW-L-K
(Sheet 2 of 2)
Description
Description
387