CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 55
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CP80617004119AES LBU3
Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet
1.CP80617004119AES_LBU3.pdf
(388 pages)
Specifications of CP80617004119AES LBU3
Lead Free Status / RoHS Status
Compliant
- Current page: 55 of 388
- Download datasheet (2Mb)
Processor Configuration Registers
1.8.10
1.8.11
Datasheet
SID - Subsystem Identification
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This value is used to identify a particular subsystem.
CAPPTR - Capabilities Pointer
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
The CAPPTR provides the offset that is the pointer to the location of the first device
capability in the capability list.
15:0
7:0
Bit
Bit
Access
Access
RW-O
RO
Default
Default
Value
0000h
Value
E0h
Subsystem ID (SUBID)
This field should be programmed during BIOS initialization.
After it has been written once, it becomes read only.
Capabilities Pointer (CAPPTR)
Pointer to the offset of the first capability ID register block. In
this case the first capability is the product-specific Capability
Identifier (CAPID0).
0/0/0/PCI
2E-2Fh
0000h
RW-O
16 bits
0/0/0/PCI
34h
E0h
RO
8 bits
Description
Description
55
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