CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 243

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.16.27
1.16.28
Datasheet
MSAC - Multi Size Aperture Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
This register determines the size of the graphics memory aperture in function 0 and in
the trusted space. Only the system BIOS will write this register based on pre- boot
address allocation efforts, but the graphics may read this register to determine the
correct aperture size. System BIOS needs to save this value on boot so that it can reset
it correctly during S3 resume.
The size of the aperture must not be modified by software after its location is written
into GMADR (offset 18h).
MC - Message Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
System software can modify bits in this register, but the device is prohibited from doing
so. If the device writes the same message multiple times, only one of those messages
is guaranteed to be serviced. If all of them must be serviced, the device must not
generate the same message again until the driver services the earlier one.
7:4
2:1
Bit
3
0
Access
RW-K
RW
RO
RO
Default
Value
01b
0h
0b
0h
Reserved
Scratch Bits Only -- Have no physical effect on
hardware
Reserved
Untrusted Aperture Size (LHSAS)
11: bits [28:27] of GMADR register are made Read
only and forced to zero, allowing only 512MB of
GMADR
01: bit [28] of GMADR is made R/W and bit [27] of
GMADR is forced to zero allowing 256MB of GMADR
00: bits [28:27] of GMADR register are made R/W
allowing 128MB of GMADR
10: Illegal programming.
These bits are read-only in Intel TXT mode.
Reserved
0/2/0/PCI
62h
02h
8 bits
0/2/0/PCI
92-93h
0000h
RO; RW
16 bits
RO; RW; RW-K;
Description
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