CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 202

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CP80617004119AES LBU3

Manufacturer Part Number
CP80617004119AES LBU3
Description
Manufacturer
Intel
Datasheet

Specifications of CP80617004119AES LBU3

Lead Free Status / RoHS Status
Compliant
1.14
1.14.1
202
Virtual Channel Enhanced Capability
Header
Port VC Capability Register 1
Port VC Capability Register 2
Port VC Control
VC0 Resource Capability
VC0 Resource Control
VC0 Resource Status
PCI Express-G Sequence
PCI Express-G Transmit De-Emphasis
Select Register
Register Name
PCI Device1 - Extended Configuration
VCECH - Virtual Channel Enhanced Capability Header
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Indicates PCI Express device Virtual Channel capabilities. Extended capability
structures for PCI Express devices are located in PCI Express extended configuration
space and have different field definitions than standard PCI capability structures.
31:20
19:16
15:0
Bit
Access
RW-O
RO
RO
Default
PEGTXDEM
Register
VC0RSTS
0002h
PVCCAP1
PVCCAP2
VC0RCAP
VC0RCTL
PEGSSTS
Value
Symbol
000h
PVCCTL
VCECH
1h
PSEL
Pointer to Next Capability (PNC)
Express extended capabilities list.
PCI Express Virtual Channel Capability Version
(PCIEVCCV)
version of the PCI Express specification. Note: This
version does not change for 2.0 compliance
Extended Capability ID (ECID)
structure) as being for PCI Express Virtual Channel
registers.
0/1/0/MMR
100-103h
00010002h
32 bits
Value of 0002 h identifies this linked list item (capability
The Link Declaration Capability is the next in the PCI
hard wired to 1 to indicate compliances with the 1.1
RW-O; RO
Register
Start
DA8
100
10C
114
11A
104
108
110
218
Register
DAB
End
10D
11B
103
107
10B
113
117
21F
Processor Configuration Registers
Description
Default Value
000000000000
00010002h
00000000h
00000000h
00000001h
43E00BF9h
800000FFh
0002h
0000h
0FFFh
RO
RW;RO
RW-O; RO
RO
RO
RO; RW
RO
RO; RW
RO
Access
Datasheet

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