CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 139

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

Processor Configuration Registers
1.10.22
Datasheet
MTDPCHOTTHINT - Memory TDP Controller Hot Throttled
Intervals
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
These registers control the duty cycle of throttling. The total throttled + non-throttled
interval can be from 32 up to 256 MCCLKS. Since throttling could be done for up to 256
clocks, 8-bit fields are needed to specify the number of clocks being throttled.
Memory will be throttled for the most number of clocks when the Hot threshold is
reached, and for progressively fewer number of mb4clks for Hot-1, Hot-2,..., Hot-7
threshold trips. The register settings should conform to this expected behavior.
31:24
23:16
15:8
7:0
Bit
Access
RW
RW
RW
RW
Default
Value
00h
00h
00h
00h
Memory IFC Hot Throttle Interval (MIHOTThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot threshold is
tripped.
Memory IFC Hot Minus 1 Throttle Interval
(MIHOTM1ThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-1 threshold is
tripped.
Memory IFC Hot Minus 2 Throttle Interval
(MIHOTM2ThrotIn)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-2 threshold is
tripped.
Memory IFC Hot Minus 3 Throttle Interval
(MIHOTM3ThrotInt)
The number of clocks, memory would be throttled for Rd
or Wr operations within the period defined by the
MITNTInt register field, when the Hot-3 threshold is
tripped.
0/0/0/MCHBAR
300-303h
00000000h
32 bits
RW
Description
139