CP80617004119AES LBU3 Intel, CP80617004119AES LBU3 Datasheet - Page 196

• Manufacturer Part Number: CP80617004119AES LBU3
• Manufacturer: Intel

Specifications of CP80617004119AES LBU3

• Lead Free Status / RoHS Status: Compliant

1.13.44
196
RCTL - Root Control
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when our
device detects an error (reported in this device's Device Status register) or when an
error message is received across the link. Reporting of SERR as controlled by these bits
takes precedence over the SERR Enable in the PCI Command Register.
15:5
Bit
4
3
2
1
0
Access
RW
RW
RW
RW
RO
RO
Default
Value
000h
0b
0b
0b
0b
0b
Reserved
Reserved for CRS Software Visibility Enable (CSVE)
This bit, when set, enables the Root Port to return
Configuration Request Retry Status (CRS) Completion Status
to software.
Root Ports that do not implement this capability must
hardwire this bit to 0b.
PME Interrupt Enable (PMEIE)
0 = No interrupts are generated as a result of receiving PME
1 = Enables interrupt generation upon receipt of a PME
System Error on Fatal Error Enable (SEFEE)
0 = Controls the Root Complex's response to fatal errors.No
1 = Indicates that an SERR should be generated if a fatal
System Error on Non-Fatal Uncorrectable Error Enable
(SENFUEE)
Controls the Root Complex's response to non-fatal errors.
0 = No SERR generated on receipt of non-fatal error.
1 = Indicates that an SERR should be generated if a non-
System Error on Correctable Error Enable (SECEE)
Controls the Root Complex's response to correctable errors.
0 = No SERR generated on receipt of correctable error.
1 = Indicates that an SERR should be generated if a
0/1/0/PCI
BC-BDh
0000h
RO; RW
16 bits
messages.
message as reflected in the PME Status bit of the Root
Status Register. A PME interrupt is also generated if the
PME Status bit of the Root Status Register is set when
this bit is set from a cleared state.
SERR generated on receipt of fatal error.
error is reported by any of the devices in the hierarchy
associated with this Root Port, or by the Root Port itself.
fatal error is reported by any of the devices in the
hierarchy associated with this Root Port, or by the Root
Port itself.
correctable error is reported by any of the devices in the
hierarchy associated with this Root Port, or by the Root
Port itself.
Processor Configuration Registers
Description
Datasheet