TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 98

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

Example when using PWM mode
Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required
Match between
TA0REG and up-counter
TA1OUT
2
(INTTA0)
n
(4) Comparator (CP0)
(5) Timer flip-flop (TA1FF)
overflow interrupt
as explained below.
If new data is written to the register buffer immediately before an overflow occurs by a
match between the timer register value and the up-counter value, the timer flip-flop may
output an unexpected value.
For this reason, make sure that in PWM mode new data is written to the register buffer by
six cycles (f
In the case of using PPG mode, make sure that new data is written to the register buffer by
six cycles before the next cycle compare match occurs by using a cycle compare match
interrupt.
register. If they match, the up counter is cleared to zero and an interrupt signal
(INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer
flip-flop is inverted at the same time.
comparator output) of each interval timer.
TA1FFCR<TA1FFIE> in the timer flip-flop control register.
bits inverts the value of TA1FF (This is known as software inversion).
pin is used as the timer output, the timer flip-flop should be set beforehand using the
port A function register PAFC2.
The comparator compares the value in an up counter with the value set in a timer
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit
Whether inversion is enabled or disabled is determined by the setting of the bit
A Reset clears the value of TA1FF1 to 0.
Writing 01 or 10 to TA1FFCR<TA1FFC1:0> sets TA1FF to 0 or 1. Writing 00 to these
The TA1FF signal is output via the TA1OUT pin (Concurrent with PA1). When this
SYS
× 6) before the next overflow occurs by using an overflow interrupt.
91C025-96
Write new data to the register buffer
before the next overflow occurs by
using an overflow interrupt
(PWM cycle)
t
PWM
Desired PWM cycle
change point
TMP91C025
2007-02-28