TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 45

• Manufacturer Part Number: TMP91xy25FG
• Manufacturer: Toshiba

Specifications of TMP91xy25FG

• Package: LQFP100
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: Ramless
• Architecture: 16-bit CISC
• Usb/spi Channels: -
• Uart/sio Channels: 2
• I2c/sio Bus Channels: -
• (s)dram Controller: -
• Adc 10-bit Channel: 4
• Da Converter: -
• Timer 8-bit Channel: 4
• Timer 16-bit Channel: -
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 49
• Power Supply Voltage(v): 3.0 to 3.6

WR
D0 to D15
A0 to A23
/
HWR
RD
X1
States 1 to 3: Instruction fetch cycle (Gets next address code).
States 4 to 5: Micro DMA read cycle
State 6:
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states.
Note 2: If the destination address area is an 8-bit bus, it is increased by two states.
priority is not based on the interrupt priority level but on the channel number. The
smaller channel number has the higher priority (Channel 0 (High) > channel 3 (Low)).
32-bit control register, this register can only effectively output 24-bit addresses.
Accordingly, micro DMA can access 16 Mbytes (the upper eight bits of the 32 bits are
not valid).
transfer, and 4-byte transfer. After a transfer in any mode, the transfer
source/destination addresses are increased, decreased, or remain unchanged.
from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) Transfer mode register.
As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to
65536 times per interrupt source. (The micro DMA processing count is maximized
when the transfer counter initial value is set to 0000H.)
start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 25
interrupts.
address INC mode (except for counter mode, the same as for other modes).
source/transfer destination addresses both even-numberd values).
If a micro DMA request is set for more than one channel at the same time, the
While the register for setting the transfer source/transfer destination addresses is a
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one word)
This simplifies the transfer of data from I/O to memory, from memory to I/O , and
Micro DMA processing can be started by the 24 interrupts shown in the micro DMA
Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination
(The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer
1 state
DM1
If the source address area is a 16-bit bus and the address starts from an odd number,
it is increased by two states.
If the destination address area is a 16-bit bus and the address starts from an odd
number, it is increased by two states.
DM2
If 3 bytes and more instruction codes are inserted in the instruction queue
buffer, this cycle becomes a dummy cycle.
Dummy cycle (the address bus remains unchanged from state 5)
Figure 3.4.2 Timing for Micro DMA Cycle
DM3
DM4
Trasfer source address
91C025-43
Note 1
Input
DM5
DM6
DM7
Trasger destination
Note 2
address
Output
DM8
TMP91C025
2007-02-28