TMP91xy25FG Toshiba, TMP91xy25FG Datasheet - Page 128

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TMP91xy25FG

Manufacturer Part Number
TMP91xy25FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP91xy25FG

Package
LQFP100
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
Ramless
Architecture
16-bit CISC
Usb/spi Channels
-
Uart/sio Channels
2
I2c/sio Bus Channels
-
(s)dram Controller
-
Adc 10-bit Channel
4
Da Converter
-
Timer 8-bit Channel
4
Timer 16-bit Channel
-
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
49
Power Supply Voltage(v)
3.0 to 3.6
Concurrent
Concurrent
Concurrent
with PC5
with PC5
with PC4
SCLK1
SCLK1
RXD1
f
φT0
SYS
I/O interface mode
SC1MOD0
<RXE>
φ
φ
φ
φ
T0
T2
T8
T32
RXDCLK
RB8
Serial clock generation circuit
Receive buffer 1 (Shift register)
2
Receive buffer 2 (SC1BUF)
<BR1CK1:0>
Figure 3.9.3 Block Diagram of the Serial Channel 1 (SIO1)
φT2
(UART only ÷ 16)
BR1CR
4
Receive
Receive
Prescaler
counter
<BR1S3:0>
control
8
BR1CR
φT8
16 32 64
Baud rate
generator
<BR1ADDE>
BR1CR
φT32
BR1ADD
<BR1K3:0>
SC1MOD0
<WU>
<OERR><PERR><FERR>
<PE>
Internal data bus
Parity control
SC1CR
Error flag
÷2
SC1CR
91C025-126
Serial channel
<EVEN>
(from TMRA0)
interrupt
TA0TRG
control
SC1MOD0
<SC1:0>
SC1CR
<IOC>
I/O
interface mode
UART
mode
SC1MOD0
TXDCLK
<SM1:0>
TB8
Transmission buffer (
(UART only ÷ 16)
Transmission
Transmision
counter
control
SIOCLK
SC1BUF)
SC1MOD0
<CTSE>
TMP91C025
2007-02-28
INT request
INTRX1
INTTX1
Concurrent
with PC5
TXD1
Concurrent
with PC3
CTS
1

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